1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device which is provided with a highly integrated LSI interconnection, and a polisher used in the method for manufacturing such semiconductor device.
2. Description of the Related Art
Cu interconnections, which are low in resistance and high in electromigration resistance, are used as CMOS-LSI interconnect materials that are being made minute and high in speed. As opposed to Al interconnections which are conventionally used, Cu interconnections are difficult to dry-etch; accordingly, a damascene process for forming an opening portion (an interconnect groove (trench) and a via hole) in an insulating film and a dual damascene process (in which a trench and a via hole are integrally formed) have been developed, and Cu interconnections are formed by these processes (as in Japanese Patent Application Laid-Open (JP-A) Nos. 2004-63996 and 2004-363464, for example).
For example, an interconnection forming method for an interconnect structure whose minimum via hole/trench diameter is 90 nm will be briefly described. An interconnect structure in which the thickness of an interconnect first layer portion (interlayer thickness) is 440 nm and the minimum via hole/trench diameter is 90 nm is formed by a single damascene process or a dual damascene process (FIG. 2A). Then a barrier metal is formed to prevent Cu from spreading onto an insulating film (FIG. 2B), and a Cu seed functioning as an electrode is formed by a PVD method (sputtering method) or a CVD method (FIG. 2C). The thickness of the barrier metal is set at approximately 5 nm to 20 nm, and the thickness of the Cu seed set at approximately 40 nm to 120 nm. Afterward, the interconnect structure undergoes electrolytic plating in a copper sulfate plating solution such that a Cu plate is deposited until it becomes 0.4 μm to 2 μm or so in thickness, and Cu is embedded in a via hole/trench (FIG. 2D). Subsequently, an unnecessary Cu layer is removed by means of chemical-mechanical polishing (CMP) which consists of two elements that are Cu dissolution (chemical) utilizing chemical reaction, and physical polishing (mechanical) (FIG. 2E). After that, an interconnect layer is capped with a cap film, thereby forming one complete layer (FIG. 2F). This process is later repeated to form a multi-layered structure.
When an interconnection is formed by polishing a Cu film in accordance with the chemical-mechanical polishing (CMP), improvement in Cu film polishing rate is a major object to achieve in order to improve throughput and reduce costs. Also, stable polishing techniques are necessary in order to limit failure caused by variation in polishing rate, decrease in yield and defects such as corrosion.
However, if a slurry containing hydrogen peroxide (H2O2) as an oxidant and a slurry containing ammonium persulfate (APS) as an oxidant are used for polishing liquids, the slurry containing hydrogen peroxide (H2O2) decreases in Cu film polishing rate when the slurry is alkaline (as shown in FIG. 3, the polishing rate is 220.7 nm/min when pH=3, whereas the polishing rate is 0 nm/min to 1 nm/min when pH=9), and the slurry containing ammonium persulfate (APS) decreases in Cu film polishing rate when the slurry is acid (as shown in FIG. 3, the polishing rate is 73.9 nm/min when pH=9, whereas the polishing rate is 19.7 nm/min when pH=3). Accordingly, an attempt was made to control the Cu film polishing rate by controlling the pH of a slurry; however, simply controlling the pH of the slurry can cause the Cu film polishing rate to decrease.
Additionally, polishing capacity of a slurry has already been maintained by keeping the oxidation-reduction potential, electric conductivity, abrasive grain concentration, etc. of the slurry within a certain range (as in JP-A No. 2003-136406, for example).